The market for FLASH memory devices offers small margins for manufacturers of memory devices. The industry is studying new manufacturing techniques and methods to improve both yield and productivity. A known technique for increasing yield comprises implementing row, column, and sector redundancy. These techniques, even if they increase the yield, also increase relatively the time used for testing the devices on wafer, for example, Electric Wafer Sort (EWS). This increase in testing time is because the test machine, besides detecting the physical position of the failed element in the array, may implement a series of procedures for mapping the failed element (row, column, sector) onto an available valid spare resource. This may limit productivity, and for improving it, further investments are made for improving the throughput of validated devices.
The devices being fabricated may be usually tested on wafer using techniques, for example, EWS, for determining the presence of failed elements (rows, columns, or whole sectors), and for repairing them by substituting the failed element with spare resources available on chip. As schematically depicted in FIG. 1A, the whole test, substitution, and verification process may be carried out by the test machine establishing communication with each single die in order to: 1. carry out specific tests for determining the presence of eventual failures; 2. store (in the test machine) the position of the failures detected in the memory array of cells; 3. apply the redundancy rules of the particular architecture (written in the software for managing the test machine) used for mapping correctly the failed element on an equivalent spare (redundancy) element; and 4. write in a nonvolatile fashion in the memory under test the information obtained in the previous steps.
This process may have two drawbacks: complex test programs may be developed for carrying out the search of and implementing complex techniques for repairing eventual failures; and the time used by the test machine for testing each single die, for determining eventual failures, and for arranging substitution by spare resources, where it is possible, may be relatively long. This resulting increase in yield due to redundancy may reduce productivity because of testing. It is possible to compensate for this reduction of productivity by buying and installing numerous test machines.
In order to improve productivity, architectures of memory devices that contemplate integrating in the same device dedicated structures for simplifying the operations carried out by the test machine have been disclosed. The prior published European patent application No. EP 1,624,465 “Programmable multi-mode built-in self-test and self-repair structure for embedded memory arrays,” in the name of Assignee of the present application, discloses an architecture developed to provide a tool for the analysis of failures that may suggest possible effective modifications of certain process conditions for reducing the number of failures. The article “Programmable Built-In Self-Testing of Embedded RAM Clusters in System-on-Chip Architectures”, by A. Benso, et al., IEEE Communications Magazine, September 2003, pages 90 to 97, provides another example of these known approaches.
These known techniques may have the drawback of using integrated complex dedicated structures, such as dedicated processors, for realizing a so-called Built In Self Test (BIST) system or, as in the case of the above mentioned prior application, for realizing a Built In Self Test and Self Repair (BISR) system. The realization of which uses silicon real estate. This may render these architectures unusable on stand alone FLASH memory devices. It may be employed in systems on chip or on complex architectures of chips that include, for commercial purposes, microcontrollers and large volatile memory arrays (RAM). Moreover, these systems may contemplate an interaction with the EWS test machine for collecting verification data when reading the memory and for carrying out redundancy operations and read operations. These operations are carried out for verifying the correct functionality of memory locations and involve the whole data path of the memory device.
On another account, modern nonvolatile FLASH memory devices (even stand alone devices) may include a small microcontroller system for managing operations of the memory, the system comprising a microprocessor and a related ROM storing program codes for executing the various functions. The system may also comprise an internal address counter, one or more auxiliary RAM memory arrays, for example, for managing the protection of sectors and for storing configuration information of the device that are read during the turn on phase, and arrays of CAMs or a reserved sector of the non volatile memory array, inaccessible by the user, in which, during a phase of test on wafer of the device being fabricated, redundancy and configuration information of the inner circuitry and other specific parameters of the device under test are permanently written.